verilog code for d-latch using dataflow

·         D LATCH USING DATAFLOW

module latch_d
(input e, D,
output Q);
assign Q=e&D;
endmodule


TESTBENCH

module latch_d_tb;
reg e,D;
wire q;
latch_d m(e,D,q);
initial
begin
e=0;D=0;
$monitor($time, ,,"e=%b",e,,"D=%b",D,,"q=%b",q);
#1 e=0;D=0;
#1 e=1;D=0;
#1 e=0;D=1;
#1 e=1;D=1;
end
endmodule

You can also check more verilog code on

http://kaneriadhaval.blogspot.in/2013/11/all-besic-verilog-code.html