verilog code for berral shifter

BERRAL SHIFTER



module bshift
(
input [7:0]a,
input [2:0]sh,
input left,right,
output reg [7:0] b);

always@(a,sh)
begin

if(left)
begin
case(sh)
3'b000: b = a;
3'b001: b = a<<1;
3'b010: b = a<<2;
3'b011: b = a<<3;
3'b100: b = a<<4;
3'b101: b = a<<5;
3'b110: b = a<<6;
3'b111: b = a<<7;
endcase
end

if(right)
begin
case(sh)
3'b000: b = a;
3'b001: b = a>>1;
3'b010: b = a>>2;
3'b011: b = a>>3;
3'b100: b = a>>4;
3'b101: b = a>>5;
3'b110: b = a>>6;
3'b111: b = a>>7;
endcase
end

end
endmodule

TESTBENCH

module bshift_tb;
reg [7:0] a;
reg [2:0] sh,left,right;
wire [7:0] b;

bshift bs(a,sh,left,right,b);

initial
begin
sh=3'b000;a=8'b11111111;left=1'b1;right=1'b0;
$monitor($time, ,"lef","ft=",left, ,"rig","ht=",right, ,"shi","ft", ,"%b",sh,  ,"inp","ut", ,"%b",a,   ,"out","put", ,"%b",b);
end

always
#1 sh=sh+1;

initial
#9 left=1'b0;
initial
#10 right=1'b1;

initial
#18 $stop;

endmodule

You can also check more verilog code on

http://kaneriadhaval.blogspot.in/2013/11/all-besic-verilog-code.html