verilog code for 16x2 mux using 2x1

16x2 MUX USING 2X1 MUX USING STRUCTRAL MODELING

module mux16to1
(
input [15:0]w,
input [3:0]s,
output wire [15:0]m,
output f);

mux2to1 mu1(m[0],w[1:0],s[0]);
mux2to1 mu2(m[1],w[3:2],s[0]);
mux2to1 mu3(m[2],w[5:4],s[0]);
mux2to1 mu4(m[3],w[7:6],s[0]);
mux2to1 mu5(m[4],w[9:8],s[0]);
mux2to1 mu6(m[5],w[11:10],s[0]);
mux2to1 mu7(m[6],w[13:12],s[0]);
mux2to1 mu8(m[7],w[15:14],s[0]);
mux2to1 mu9(m[8],m[1:0],s[1]);
mux2to1 mu10(m[9],m[3:2],s[1]);
mux2to1 mu11(m[10],m[5:4],s[1]);
mux2to1 mu12(m[11],m[7:6],s[1]);
mux2to1 mu13(m[12],m[9:8],s[2]);
mux2to1 mu14(m[13],m[11:10],s[2]);
mux2to1 mu15(f,m[13:12],s[3]);

endmodule

module mux2to1
(
output f,
input [1:0]w,sel
);
and m1(x,w[0],~sel);
and m2(y,w[1],sel);
or m3(f,x,y);
endmodule

TESTBENCH

module mux16to1_tb;

reg [15:0]w;
reg [3:0]s;
wire [15:0]m;
wire f;

mux16to1 m16to1(w,s,m,f);

initial
begin
w=16'b1010101010101010;
s=4'b0000;
$monitor($time, ,"inp",   ,"%b",w,  ,"sel", ,"%b",s,  ,"out", ,f);

end
always
#1 s=s+1;

initial
#16 $stop;
endmodule

You can also check more verilog code on

http://kaneriadhaval.blogspot.in/2013/11/all-besic-verilog-code.html