Thursday 14 November 2013

verilog code for washing machine

hello guys....

i am providing u a verilog code for washing machine with testbench....




WASHING MACHINE

module wm(clk,rst,coin, lid_r, d_wash, T, soak,rinse, spin, wash,pause,break);
 input clk,rst,coin,lid_r,d_wash,T;
 output reg soak,rinse,spin,wash,pause,break;
 reg[2:0] cst, nst;

 // state assignment
 parameter IDLE = 3'b000,
           SOAK = 3'b001,
             WASH=3'b010,
             RINSE=3'b011,
             WASH2=3'b100,
             RINSE2=3'b101,
             SPIN=3'b110,
             PAUSH=3'b111;

always @(cst or coin or d_wash or lid_r or T)
begin
   case (cst)
     IDLE:
if(coin==1)
          begin
          nst=SOAK;
          soak=1;
          rinse=0;
          spin=0;
          wash=0;
          pause=0;
          break=0;
          end
else

          begin
          nst=cst;
          soak=0;
          rinse=0;
          spin=0;
          wash=0;
          pause=0;
          break=0;
          end

SOAK:
if(T==1)

          begin
          nst=WASH;
          soak=0;
          rinse=0;
          spin=0;
          wash=1;
          pause=0;
          break=0;
          end
else
          begin
          nst=cst;
          soak=1;
          rinse=0;
          spin=0;
          wash=0;
          pause=0;
          break=0;
          end
     WASH:
if(T==1)

          begin
          nst=RINSE;
          soak=0;
          rinse=1;
          spin=0;
          wash=0;
          pause=0;
          break=0;
          end
else
          begin
          nst=cst;
          soak=0;
          rinse=0;
          spin=0;
          wash=1;
          pause=0;
          break=0;
          end
RINSE:
if(T==1 && d_wash==1)

          begin
          nst=WASH2;
          soak=0;
          rinse=0;
          spin=0;
          wash=1;
          pause=0;
          break=0;
          end
else if(T==1 && d_wash==0)

          begin
          nst=SPIN;
          soak=0;
          rinse=0;
          spin=1;
          wash=0;
          pause=0;
          break=0;
          end
else
          begin
          nst=cst;
          soak=0;
          rinse=1;
          spin=0;
          wash=0;
          pause=0;
          break=0;
          end
WASH2:
if(T==1)

          begin
          nst=RINSE2;
          soak=0;
          rinse=1;
          spin=0;
          wash=0;
          pause=0;
          break=0;
          end
else
          begin
          nst=cst;
          soak=0;
          rinse=0;
          spin=0;
          wash=1;
          pause=0;
          break=0;
          end

RINSE2:
if(T==1)
          begin
          nst=SPIN;
          soak=0;
          rinse=0;
          spin=1;
          wash=0;
          pause=0;
          break=0;
          end
else
          begin
          nst=cst;
          soak=0;
          rinse=1;
          spin=0;
          wash=0;
          pause=0;
          break=0;
          end
SPIN:
if(T==0 && lid_r==1)
          begin
          nst=PAUSH;
          soak=0;
          rinse=0;
          spin=0;
          wash=0;
          pause=1;
          break=0;
          end
else if(T==1)
          begin
          nst=IDLE;
          soak=0;
          rinse=0;
          spin=0;
          wash=0;
          pause=0;
          break=0;
          end
else
          begin
          nst=cst;
          soak=0;
          rinse=0;
          spin=1;
          wash=0;
          pause=0;
          break=0;
          end
PAUSH:
if(lid_r==0)
          begin
          nst=SPIN;
          soak=0;
          rinse=0;
          spin=1;
          wash=0;
          pause=0;
          break=0;
          end
else
          begin
          nst=cst;
          soak=0;
          rinse=0;
          spin=0;
          wash=0;
          pause=1;
          break=0;
          end
     default:
nst=IDLE;
   endcase
  end
always @(posedge clk or negedge rst)
begin
   if (rst)
     cst <= IDLE;
    else
     cst <= nst;
 end
/*
  assign soak = (cst == SOAK);
  assign rinse = (cst == RINSE) | (cst == RINSE2);
  assign brake = (cst == PAUSE);
  assign spin = (cst == SPIN);
  assign wash = (cst == WASH) | (cst == WASH2);
*/
endmodule

TEST BENCH

module wm_tb;
reg clk,reset,coin,lid_r,d_wash,T;
wire soak,rinse,spin,wash,pause,break;
wm m1(clk,reset,coin,lid_r,d_wash,T,soak,rinse,spin,wash,pause,break);
initial
begin

$monitor($time, ,,"c=%b",clk,,"t=%b",coin,,"l=%b",lid_r,,"d=%b",d_wash,,"T=%b",T,,"s=%b",soak,,"r=%b",rinse,,"S=%b",spin,,"w=%b",wash,,"p=%b",pause,,"b=%b",break);
reset=0       ;clk=0;coin=0;lid_r=0;d_wash=0;T=0;
#10 coin=1;
#10 T=1;coin=0;
#20 d_wash=1;
#30 lid_r=1;d_wash=0;T=0;
#10 lid_r=0;T=0;
#10 T=1;lid_r=0;
#10 T=1;
#10 coin=1;T=0;
//#10 T=1;
//#10 T=1;
//#5 reset=1;
//#5 reset=0;
end
always
#5 clk=~clk;
initial
#100 $finish ;

endmodule

33 comments:

  1. Gud one...modify your code for standard design :
    If you use logic high for reset then use posedge reset statement in always block...!!!
    define task in test-bench for repetitive control signal.
    always disable all control signal in start of always block in FSM design.

    ReplyDelete
    Replies
    1. ya...i tried during practice...........but during upload i changed it....so sorry for that....i put reset on neg edge during practice.....

      Delete
    2. i put here only for reference purpose....u can modify accordingly.......

      Delete
    3. dear dhaval,
      i have an urgent requirement ,if u dont mind plz send to my mail id (yedunath.k@gmail.com) following details as per above verilog
      1-state diagram
      2-transition table
      3-excitation table
      4-kmap
      5-circuit

      Delete
    4. can we imlement this in bassy3 board

      Delete
  2. how can i implement it in FPGA development board

    ReplyDelete
    Replies
    1. I had implement it on Xilinx FPGA board. In your case you need to configure toggle button for input and for output u can watch out led pin number from your respective FPGA board and then dump code through any JTAG connector.

      Delete
  3. This comment has been removed by the author.

    ReplyDelete
    Replies
    1. This comment has been removed by the author.

      Delete
  4. Can you pls provide me vhdl code for washing machine controller for my project on my email id ramayadav1970@gmail.com its urgent.

    ReplyDelete
  5. nice work dhaval keep doing bro

    ReplyDelete
  6. hey I am trying to implement md5 in my code please help me getting some wrong hash value for more please contact me on akshayamj4@gmail.com

    ReplyDelete
  7. hey ...can u plz me state machine explaintation please

    ReplyDelete
  8. hamza.687@gmail.com can you please send me whole code on my email. Th one you use for yourself in final stage. I need your help to for teaching me few things related to that i will pay you for teaching me

    ReplyDelete
  9. hi. i run your code, but then there an error at this phase: line if (nst)

    always @(posedge clk or negedge rst)
    begin
    if (nst)
    cst <= IDLE;
    else
    cst <= nst;
    end

    Can you explain why?

    ReplyDelete
    Replies
    1. remove the negedge rst and it should be fine

      Delete
  10. This comment has been removed by the author.

    ReplyDelete
  11. can you also share how does the waveform look like for this verilog coding. my email is afrafathimah001101@gmail.com

    ReplyDelete
  12. can you also share how does the waveform look like for this verilog coding. my email is lanjiocb8@gmail.com

    ReplyDelete
  13. can i know what is lid r stand for

    ReplyDelete
  14. can i know what is lid r and coin stand for

    ReplyDelete
  15. Washing machine service in dubai
    https://www.hometech.ae/service/washing-machine-service/
    UAEs Authorized Major brand Washing Machine Service in Dubai, On-Demand experienced professionals for washing machine service in Dubai.
    1632380306853-9

    ReplyDelete
  16. Sir, can you please tell what is lid_r stands for?and can you please provide it's output also..

    ReplyDelete
  17. dear dhaval,
    i have an urgent requirement ,if u dont mind plz send to my mail id (syiqin.ciken97@gmail.com) following details as per above verilog
    1-state diagram
    2-transition table
    3-excitation table
    4-kmap
    5-circuit
    6-procedure to implement to fpga board
    7- full report for this project

    ReplyDelete
  18. dear dhaval,
    i have an urgent requirement ,if u dont mind plz send to my mail id (azfarhaniff1@gmail.com) following details as per above verilog
    1-state diagram
    2-transition table
    3-excitation table
    4-kmap
    5-circuit
    6-procedure to implement to fpga board
    7- full report for this project

    ReplyDelete