verilog code for mejority detector

MEJORITY DETECTOR

module majority
(input v1,v2,v3,
output reg m);
always@(v1 or v2 or v3)
begin
            if((v1&&v2)|(v2&&v3)|(v3&&v1))
            m=1;
            else
            m=0;
end
endmodule

TESTBENCH

module majority_tb;
reg v1,v2,v3;
wire m;
majority m1(v1,v2,v3,m);
initial
begin
v1=0;v2=0;v3=0;
$monitor($time, ,,v1,v2,v3,,"m=%d",m);
#2 v1=0;v2=0;v3=0;
#2 v1=0;v2=0;v3=1;
#2 v1=0;v2=1;v3=1;
#2 v1=1;v2=0;v3=0;
#2 v1=1;v2=0;v3=1;
#2 v1=1;v2=1;v3=0;
#2 v1=1;v2=1;v3=1;
end
endmodule

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verilog code for counter

COUNTER INCREMENT BY 2

module counter2(r,clk,y);
input r,clk;
output [3:0]y;
reg [3:0]y;
always@(posedge clk or posedge r)
begin
if (r)
y <= 4'b0000;
else
y <= y + 2;
end
endmodule

TESTBENCH

module counter3_tb;
reg r,clk;
wire [3:0]y;
counter2 m1(r,clk,y);
initial
begin
clk=0;
r=0;
$monitor($time, ,,"c=%b",clk,,"r=%b",r,,"y=%b",y);
#5 r=1;
#15 r=0;
#50 $finish;
end
always
begin
#5 clk=~clk;
end
endmodule

OUTPUT



·         COUNTER INCREMENT BY 3

module counter2(r,clk,y);
input r,clk;
output [3:0]y;
reg [3:0]y;
always@(posedge clk or posedge r)
begin
if (r)
y <= 4'b0000;
else
y <= y + 3;
end
endmodule

TESTBENCH

module counter3_tb;
reg r,clk;
wire [3:0]y;
counter2 m1(r,clk,y);
initial
begin
clk=0;
r=0;
$monitor($time, ,,"c=%b",clk,,"r=%b",r,,"y=%b",y);
#5 r=1;
#15 r=0;
#50 $finish;
end
always
begin
#5 clk=~clk;
end
endmodule

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verilog code for berral shifter

BERRAL SHIFTER



module bshift
(
input [7:0]a,
input [2:0]sh,
input left,right,
output reg [7:0] b);

always@(a,sh)
begin

if(left)
begin
case(sh)
3'b000: b = a;
3'b001: b = a<<1;
3'b010: b = a<<2;
3'b011: b = a<<3;
3'b100: b = a<<4;
3'b101: b = a<<5;
3'b110: b = a<<6;
3'b111: b = a<<7;
endcase
end

if(right)
begin
case(sh)
3'b000: b = a;
3'b001: b = a>>1;
3'b010: b = a>>2;
3'b011: b = a>>3;
3'b100: b = a>>4;
3'b101: b = a>>5;
3'b110: b = a>>6;
3'b111: b = a>>7;
endcase
end

end
endmodule

TESTBENCH

module bshift_tb;
reg [7:0] a;
reg [2:0] sh,left,right;
wire [7:0] b;

bshift bs(a,sh,left,right,b);

initial
begin
sh=3'b000;a=8'b11111111;left=1'b1;right=1'b0;
$monitor($time, ,"lef","ft=",left, ,"rig","ht=",right, ,"shi","ft", ,"%b",sh,  ,"inp","ut", ,"%b",a,   ,"out","put", ,"%b",b);
end

always
#1 sh=sh+1;

initial
#9 left=1'b0;
initial
#10 right=1'b1;

initial
#18 $stop;

endmodule

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verilog code for 16x2 mux using 2x1

16x2 MUX USING 2X1 MUX USING STRUCTRAL MODELING

module mux16to1
(
input [15:0]w,
input [3:0]s,
output wire [15:0]m,
output f);

mux2to1 mu1(m[0],w[1:0],s[0]);
mux2to1 mu2(m[1],w[3:2],s[0]);
mux2to1 mu3(m[2],w[5:4],s[0]);
mux2to1 mu4(m[3],w[7:6],s[0]);
mux2to1 mu5(m[4],w[9:8],s[0]);
mux2to1 mu6(m[5],w[11:10],s[0]);
mux2to1 mu7(m[6],w[13:12],s[0]);
mux2to1 mu8(m[7],w[15:14],s[0]);
mux2to1 mu9(m[8],m[1:0],s[1]);
mux2to1 mu10(m[9],m[3:2],s[1]);
mux2to1 mu11(m[10],m[5:4],s[1]);
mux2to1 mu12(m[11],m[7:6],s[1]);
mux2to1 mu13(m[12],m[9:8],s[2]);
mux2to1 mu14(m[13],m[11:10],s[2]);
mux2to1 mu15(f,m[13:12],s[3]);

endmodule

module mux2to1
(
output f,
input [1:0]w,sel
);
and m1(x,w[0],~sel);
and m2(y,w[1],sel);
or m3(f,x,y);
endmodule

TESTBENCH

module mux16to1_tb;

reg [15:0]w;
reg [3:0]s;
wire [15:0]m;
wire f;

mux16to1 m16to1(w,s,m,f);

initial
begin
w=16'b1010101010101010;
s=4'b0000;
$monitor($time, ,"inp",   ,"%b",w,  ,"sel", ,"%b",s,  ,"out", ,f);

end
always
#1 s=s+1;

initial
#16 $stop;
endmodule

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verilog code for 4 -bit ripple carry adder using full adder

 4-BIT RIPPLE CARRY ADDER USING FULL ADDER

           
module rip2(s,cout,a,b,cin);
  input [3:0]a;
  input [3:0]b;
  input cin;
  output cout;
  output [3:0]s;
  wire c2,c3,c4,cout;
  fa m1(s[0],c2,a[0],b[0],cin);
  fa m2(s[1],c3,a[1],b[1],c2);
  fa m3(s[2],c4,a[2],b[2],c3);
  fa m4(s[3],cout,a[3],b[3],c4);
endmodule

TESTBENCH

module fa(s,cout,a,b,cin);
input a,b,cin;
output s,cout;
wire w1,w2,w3;
ha m1(w1,w2,a,b);
ha m2(s,w3,w1,cin);
or m3(cout,w2,w3);
endmodule

module ha(s,cout,a,b);      //sub module for Half adder
  input a,b;
  output s,cout;
  xor m1(s,a,b);
  and m2(cout,a,b);
endmodule

module rip2_tb;
reg [3:0]a;
reg [3:0]b;
reg cin;
wire cout;
wire [3:0]s;
rip2 m1(s,cout,a,b,cin);
initial
begin
a=4'b0000;b=4'b0000;cin=0;
$monitor($time, ,,"a=%b",a,,"b=%b",b,,"c=%b",cin,,"d=%b",cout,,"s=%b",s);
#5 a=4'b0000;b=4'b0000;cin=0;
#5 a=4'b0001;b=4'b0000;cin=1;
#5 a=4'b1100;b=4'b1100;cin=1;
#5 a=4'b1100;b=4'b1100;cin=0;
#5 a=4'b1101;b=4'b1101;cin=1;
#5 a=4'b0001;b=4'b1000;cin=1;
#5 a=4'b0000;b=4'b1111;cin=1;
#5 a=4'b1100;b=4'b1100;cin=0;
#5 a=4'b0000;b=4'b0111;cin=1;
#5 a=4'b1100;b=4'b0010;cin=1;
end
endmodule

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verilod code for n-bit binary to gray converter

-BIT BINARY TO GRAY CONVERTER

module binary2gray #(parameter n=4)
(
input [n-1:0] b,
output [n-1:0] g     
);
assign g={b[n],b[n:1]^b[n-1:0]};
endmodule

TESTBENCH

module binary2gray_tb;
parameter n=4;
reg [n-1:0]b;
wire [n-1:0]g;
binary2gray b2g(b,g);
initial
begin
#1 b=4'b1111;
$monitor($time,  ,"bin","ary=","%b",b, ,"gra","y=","%b",g);
end

always

#1 b=b+1;

initial
#10 $stop;
endmodule

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verilog code for n-bit gray to binary converter

N-BIT  GRAY TO BINARY CONVERTER

module binary2gray #(parameter n=4)
(
input [n-1:0] g,
output [n-1:0] b
);
assign b={g[n],b[n:1]^g[n-1:0]};
endmodule

TESTBENCH

module binary2gray_tb;
parameter n=4;
reg [n-1:0]g;
wire [n-1:0]b;
binary2gray b2g(.b(b),.g(g));
initial
begin
#1 g=4'b1111;
$monitor($time,  ,"gra","y","%b",g, ,"bin","ary","%b",b);
end

always

#1 g=g+1;

initial
#10 $stop;
endmodule

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verilog code for d-latch using dataflow

·         D LATCH USING DATAFLOW

module latch_d
(input e, D,
output Q);
assign Q=e&D;
endmodule


TESTBENCH

module latch_d_tb;
reg e,D;
wire q;
latch_d m(e,D,q);
initial
begin
e=0;D=0;
$monitor($time, ,,"e=%b",e,,"D=%b",D,,"q=%b",q);
#1 e=0;D=0;
#1 e=1;D=0;
#1 e=0;D=1;
#1 e=1;D=1;
end
endmodule

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verilog code for bcd to binary

BCD TO BINARY


module bcd2binary
(input [7:0]bcd,
output reg[3:0]binary);

always@(bcd)
begin
if(bcd[3:0]<4'b1010)
begin
if(bcd[7:4]=={4{1'b0}})
binary=bcd[3:0];
if((bcd[7:5]=={3{1'b0}})&&(bcd[4]==1'b1))
binary=bcd[3:0]+4'b1010;
end
else
binary={4{1'bx}};

end
endmodule

TEST BENCH

module bcd2binary_tb;
reg [7:0]bcd;
wire [3:0]binary;

bcd2binary b1(bcd,binary);
initial
begin
bcd=8'b00000000;
$monitor($time, ,"bcd", ,"%b",bcd,  , "bin","ary", ,"%b",binary);
end

always
#1 bcd=bcd+1;

initial
#22 $stop;
endmodule

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32-BIT BARREL SHIFTER IN VERILOG

32-BIT BARREL SHIFTER

module barrel (
input [n:0]in,
input [4:0]sh,
input shift_LeftRight,rotate_LeftRight,
output reg [n:0] out);
parameter n=31;
always@*
begin
if(~shift_LeftRight)
out = in<<sh;
else if(shift_LeftRight)
out = in>>sh;
else
begin
case(sh)
5'b00001:
out=(~rotate_LeftRight)?{in[n-1:0],in[n]}:{in[0],in[n:1]};
5'b00010:
out=(~rotate_LeftRight)?{in[n-2:0],in[n:n-1]}:{in[1:0],in[n:2]};
5'b00011:
out=(~rotate_LeftRight)?{in[n-3:0],in[n:n-2]}:{in[2:0],in[n:3]};
5'b00100:
out=(~rotate_LeftRight)?{in[n-4:0],in[n:n-3]}:{in[3:0],in[n:4]};
5'b00101:
out=(~rotate_LeftRight)?{in[n-5:0],in[n:n-4]}:{in[4:0],in[n:5]};
5'b00110:
out=(~rotate_LeftRight)?{in[n-6:0],in[n:n-5]}:{in[5:0],in[n:6]};
5'b00111:
out=(~rotate_LeftRight)?{in[n-7:0],in[n:n-6]}:{in[6:0],in[n:7]};
5'b01000:
out=(~rotate_LeftRight)?{in[n-8:0],in[n:n-7]}:{in[7:0],in[n:8]};
5'b01001:
out=(~rotate_LeftRight)?{in[n-9:0],in[n:n-8]}:{in[8:0],in[n:9]};
5'b01010:
out=(~rotate_LeftRight)?{in[n-10:0],in[n:n-9]}:{in[9:0],in[n:10]};
5'b01011:
out=(~rotate_LeftRight)?{in[n-11:0],in[n:n-10]}:{in[10:0],in[n:11]};
5'b01100:
out=(~rotate_LeftRight)?{in[n-12:0],in[n:n-11]}:{in[11:0],in[n:12]};
5'b01101:
out=(~rotate_LeftRight)?{in[n-13:0],in[n:n-12]}:{in[12:0],in[n:13]};
5'b01110:
out=(~rotate_LeftRight)?{in[n-14:0],in[n:n-13]}:{in[13:0],in[n:14]};
5'b01111:
out=(~rotate_LeftRight)?{in[n-15:0],in[n:n-14]}:{in[14:0],in[n:15]};
5'b10000:
out=(~rotate_LeftRight)?{in[n-16:0],in[n:n-15]}:{in[15:0],in[n:16]};
5'b10001:
out=(~rotate_LeftRight)?{in[n-17:0],in[n:n-16]}:{in[16:0],in[n:17]};
5'b10010:
out=(~rotate_LeftRight)?{in[n-18:0],in[n:n-17]}:{in[17:0],in[n:18]};
5'b10011:
out=(~rotate_LeftRight)?{in[n-19:0],in[n:n-18]}:{in[18:0],in[n:19]};
5'b10100:
out=(~rotate_LeftRight)?{in[n-20:0],in[n:n-19]}:{in[19:0],in[n:20]};
5'b10101:
out=(~rotate_LeftRight)?{in[n-21:0],in[n:n-20]}:{in[20:0],in[n:21]};
5'b10110:
out=(~rotate_LeftRight)?{in[n-22:0],in[n:n-21]}:{in[21:0],in[n:22]};
5'b10111:
out=(~rotate_LeftRight)?{in[n-23:0],in[n:n-22]}:{in[22:0],in[n:23]};
5'b11000:
out=(~rotate_LeftRight)?{in[n-24:0],in[n:n-23]}:{in[23:0],in[n:24]};
5'b11001:
out=(~rotate_LeftRight)?{in[n-25:0],in[n:n-24]}:{in[24:0],in[n:25]};
5'b11010:
out=(~rotate_LeftRight)?{in[n-26:0],in[n:n-25]}:{in[25:0],in[n:26]};
5'b11011:
out=(~rotate_LeftRight)?{in[n-27:0],in[n:n-26]}:{in[26:0],in[n:27]};
5'b11100:
out=(~rotate_LeftRight)?{in[n-28:0],in[n:n-27]}:{in[27:0],in[n:28]};
5'b11101:
out=(~rotate_LeftRight)?{in[n-29:0],in[n:n-28]}:{in[28:0],in[n:29]};
5'b11110:
out=(~rotate_LeftRight)?{in[n-30:0],in[n:n-29]}:{in[29:0],in[n:30]};
5'b11111:
out=(~rotate_LeftRight)?{in[n-31:0],in[n:n-30]}:{in[30:0],in[n:31]};

default:
out=in;

endcase
end
end
endmodule


`timescale 1ns / 1ps

module barrel_tb #(parameter n=31)();
reg [n:0]in;
reg [5:0]sh;
reg shift_LeftRight,rotate_LeftRight;
wire [n:0] out;
barrel bs(.in(in),.sh(sh),.shift_LeftRight(shift_LeftRight),.rotate_LeftRight(rotate_LeftRight),.out(out));
initial
begin
#1 in=32'b11111111111111110000000000000000;sh=5'b00000;rotate_LeftRight=1'b1;shift_LeftRight=1'bx;

#1 sh=5'b00001;
#1 sh=5'b00010;
#1 sh=5'b00011;
#1 sh=5'b00100;
#1 sh=5'b00101;
#1 sh=5'b00110;
#1 sh=5'b00111;
#1 sh=5'b00000;in=32'b11111111111111110000000000000000;rotate_LeftRight=1'b0;

#1 sh=5'b00001;
#1 sh=5'b00010;
#1 sh=5'b00011;
#1 sh=5'b00100;
#1 sh=5'b00101;
#1 sh=5'b00110;

#1 sh=5'b00000;in=32'b11111111111111110000000000000000;rotate_LeftRight=1'bx;shift_LeftRight=1'b0;

#1 sh=5'b00001;
#1 sh=5'b00010;
#1 sh=5'b00011;
#1 sh=5'b00100;
#1 sh=5'b00101;
#1 sh=5'b00110;

#1 sh=5'b00000;in=32'b11111111111111110000000000000000;shift_LeftRight=1'b1;
#1 sh=5'b00001;
#1 sh=5'b00010;
#1 sh=5'b00011;
#1 sh=5'b00100;
#1 sh=5'b00101;
#1 sh=5'b00110;

end
initial
#32 $finish;

                initial begin
                                // Initialize Inputs
                                in = 0;
                                sh = 0;
                                shift_LeftRight = 0;
                                rotate_LeftRight = 0;

                                // Wait 100 ns for global reset to finish
                                #100;
       
                                // Add stimulus here

                end

endmodule