Thursday, 14 November 2013

verilog code for candy vending machine

hello friends....
I am providing u verilog code for candy vending machine with test bench.





CANDY MACHINE

module candy(d,n,q, reset, clk, y);
output reg y;
input d,n,q;    //n=5,d=10,q=25;
input clk;
input reset;
reg [2:0] cst, nst;
parameter S0 = 3'b000,
          S1 = 3'b001,
          S2 = 3'b010,
          S3 = 3'b100,
              S4 = 3'b101,
              S5 = 3'b110,
              S6 = 3'b111;
always @(cst or d or n or q)
 begin
 case (cst)
   S0: if (n== 1'b1 && d==1'b0 && q==1'b0)
            begin
         nst = S1;
             y=1'b0;
            end
      else if(n== 1'b0 && d==1'b1 && q==1'b0)
            begin
            nst=S2;
            y=1'b0;
            end
            else if(n== 1'b0 && d==1'b0 && q==1'b1)
            begin
            nst=S5;
            y=1'b0;
            end
             else
            begin
            nst = cst;
            y=1'b0;
            end
   S1: if (n== 1'b1 && d==1'b0 && q==1'b0)
            begin
         nst = S2;
             y=1'b0;
            end
      else if(n== 1'b0 && d==1'b1 && q==1'b0)
            begin
            nst=S3;
            y=1'b0;
            end
            else if(n== 1'b0 && d==1'b0 && q==1'b1)
            begin
            nst=S6;
            y=1'b0;
            end
             else
            begin
            nst = cst;
            y=1'b0;
            end
   S2:if (n== 1'b1 && d==1'b0 && q==1'b0)
            begin
         nst = S3;
             y=1'b0;
            end
      else if(n== 1'b0 && d==1'b1 && q==1'b0)
            begin
            nst=S4;
            y=1'b0;
            end
            else if(n== 1'b0 && d==1'b0 && q==1'b1)
            begin
            nst=S0;
            y=1'b1;
            end
             else
            begin
            nst = cst;
            y=1'b0;
            end
   S3: if (n== 1'b1 && d==1'b0 && q==1'b0)
            begin
         nst = S4;
             y=1'b0;
            end
      else if(n== 1'b0 && d==1'b1 && q==1'b0)
            begin
            nst=S5;
            y=1'b0;
            end
            else if(n== 1'b0 && d==1'b0 && q==1'b1)
            begin
            nst=S0;
            y=1'b1;
            end
             else
            begin
            nst = cst;
            y=1'b0;
            end
S4: if (n== 1'b1 && d==1'b0 && q==1'b0)
            begin
         nst = S5;
             y=1'b0;
            end
      else if(n== 1'b0 && d==1'b1 && q==1'b0)
            begin
            nst=S6;
            y=1'b0;
            end
            else if(n== 1'b0 && d==1'b0 && q==1'b1)
            begin
            nst=S0;
            y=1'b1;
            end
             else
            begin
            nst = cst;
            y=1'b0;
            end
S5: if (n== 1'b1 && d==1'b0 && q==1'b0)
            begin
         nst = S6;
             y=1'b0;
            end
      else if(n== 1'b0 && d==1'b1 && q==1'b0)
            begin
            nst=S0;
            y=1'b1;
            end
            else if(n== 1'b0 && d==1'b0 && q==1'b1)
            begin
            nst=S0;
            y=1'b1;
            end
             else
            begin
            nst = cst;
            y=1'b0;
            end
S6: if (n== 1'b1 && d==1'b0 && q==1'b0)
            begin
         nst =S0;
             y=1'b1;
            end
      else if(n== 1'b0 && d==1'b1 && q==1'b0)
            begin
            nst=S0;
            y=1'b1;
            end
            else if(n== 1'b0 && d==1'b0 && q==1'b1)
            begin
            nst=S0;
            y=1'b1;
            end
             else
            begin
            nst = cst;
            y=1'b0;
            end
                       
   default: nst = S0;
  endcase
end
always@(posedge clk) //or posedge reset)
begin
 if (reset)
   cst <= S0;
 else
   cst <= nst;
end
endmodule

TEST BENCH

module candy_tb;
reg n,d,q,clk,reset;
wire y;
candy m1(n,d,q,reset, clk, y);
initial
begin
reset=0          ;clk=0;n=0;q=0;d=0;
$monitor($time, , ,"c=%b",clk,,"y=%b",y,,"r=%b",reset,,"d=%b",d,,"n=%b",n,,"q=%b",q);
#10 d=0;n=1;q=0;
#10 d=1;n=0;q=0;
#10 d=1;n=0;q=0;
#10 d=0;n=1;q=0;
#10 d=0;n=1;q=0;
#10 d=0;n=1;q=0;
#10 d=0;n=1;q=0;
#10 d=0;n=1;q=0;
#10 d=0;n=0;q=0;
end
always
#5 clk=~clk;
initial
#100 $finish ;

endmodule

6 comments:

  1. Could you please explain the output

    ReplyDelete
    Replies
    1. It is very simple. You can consider n = $5 ,d =$10 ,q=$25 . here three input available so 7 state will possible. Candy will generate on >=$35 . Now you have to start S0 state and check three condition of n,d,and q and check what will be next state.Every state tx. happen at $5. Ex. First you are in state S0 .now u enter n = $5 then next state will be S1. Now u enter q =$25 so next state will be S6( $25 means 5 state ahead).now u will enter n or q or d then output y = 1 and next state is reset to S0. Same way every scenario u can consider.

      Delete
    2. I made state diagram above. So it will be easy for u to understand.

      Delete
    3. could you please send verilog code for vending 4 items like candy,coffee,ice cream,coke.

      Delete

  2. Great, Thank you for sharing with us. Very nice article & have great information.

    candy vending machines

    ReplyDelete

  3. Awesome, I really like your post because the information which you given in this blog is really extra ordinary.

    vending machine business

    ReplyDelete