verilog code for 16x2 mux using 2x1

16x2 MUX USING 2X1 MUX USING STRUCTRAL MODELING

module mux16to1
(
input [15:0]w,
input [3:0]s,
output wire [15:0]m,
output f);

mux2to1 mu1(m[0],w[1:0],s[0]);
mux2to1 mu2(m[1],w[3:2],s[0]);
mux2to1 mu3(m[2],w[5:4],s[0]);
mux2to1 mu4(m[3],w[7:6],s[0]);
mux2to1 mu5(m[4],w[9:8],s[0]);
mux2to1 mu6(m[5],w[11:10],s[0]);
mux2to1 mu7(m[6],w[13:12],s[0]);
mux2to1 mu8(m[7],w[15:14],s[0]);
mux2to1 mu9(m[8],m[1:0],s[1]);
mux2to1 mu10(m[9],m[3:2],s[1]);
mux2to1 mu11(m[10],m[5:4],s[1]);
mux2to1 mu12(m[11],m[7:6],s[1]);
mux2to1 mu13(m[12],m[9:8],s[2]);
mux2to1 mu14(m[13],m[11:10],s[2]);
mux2to1 mu15(f,m[13:12],s[3]);

endmodule

module mux2to1
(
output f,
input [1:0]w,sel
);
and m1(x,w[0],~sel);
and m2(y,w[1],sel);
or m3(f,x,y);
endmodule

TESTBENCH

module mux16to1_tb;

reg [15:0]w;
reg [3:0]s;
wire [15:0]m;
wire f;

mux16to1 m16to1(w,s,m,f);

initial
begin
w=16'b1010101010101010;
s=4'b0000;
$monitor($time, ,"inp",   ,"%b",w,  ,"sel", ,"%b",s,  ,"out", ,f);

end
always
#1 s=s+1;

initial
#16 $stop;
endmodule

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verilog code for 4 -bit ripple carry adder using full adder

 4-BIT RIPPLE CARRY ADDER USING FULL ADDER

           
module rip2(s,cout,a,b,cin);
  input [3:0]a;
  input [3:0]b;
  input cin;
  output cout;
  output [3:0]s;
  wire c2,c3,c4,cout;
  fa m1(s[0],c2,a[0],b[0],cin);
  fa m2(s[1],c3,a[1],b[1],c2);
  fa m3(s[2],c4,a[2],b[2],c3);
  fa m4(s[3],cout,a[3],b[3],c4);
endmodule

TESTBENCH

module fa(s,cout,a,b,cin);
input a,b,cin;
output s,cout;
wire w1,w2,w3;
ha m1(w1,w2,a,b);
ha m2(s,w3,w1,cin);
or m3(cout,w2,w3);
endmodule

module ha(s,cout,a,b);      //sub module for Half adder
  input a,b;
  output s,cout;
  xor m1(s,a,b);
  and m2(cout,a,b);
endmodule

module rip2_tb;
reg [3:0]a;
reg [3:0]b;
reg cin;
wire cout;
wire [3:0]s;
rip2 m1(s,cout,a,b,cin);
initial
begin
a=4'b0000;b=4'b0000;cin=0;
$monitor($time, ,,"a=%b",a,,"b=%b",b,,"c=%b",cin,,"d=%b",cout,,"s=%b",s);
#5 a=4'b0000;b=4'b0000;cin=0;
#5 a=4'b0001;b=4'b0000;cin=1;
#5 a=4'b1100;b=4'b1100;cin=1;
#5 a=4'b1100;b=4'b1100;cin=0;
#5 a=4'b1101;b=4'b1101;cin=1;
#5 a=4'b0001;b=4'b1000;cin=1;
#5 a=4'b0000;b=4'b1111;cin=1;
#5 a=4'b1100;b=4'b1100;cin=0;
#5 a=4'b0000;b=4'b0111;cin=1;
#5 a=4'b1100;b=4'b0010;cin=1;
end
endmodule

You can also check more verilog code on

http://kaneriadhaval.blogspot.in/2013/11/all-besic-verilog-code.html

verilod code for n-bit binary to gray converter

-BIT BINARY TO GRAY CONVERTER

module binary2gray #(parameter n=4)
(
input [n-1:0] b,
output [n-1:0] g     
);
assign g={b[n],b[n:1]^b[n-1:0]};
endmodule

TESTBENCH

module binary2gray_tb;
parameter n=4;
reg [n-1:0]b;
wire [n-1:0]g;
binary2gray b2g(b,g);
initial
begin
#1 b=4'b1111;
$monitor($time,  ,"bin","ary=","%b",b, ,"gra","y=","%b",g);
end

always

#1 b=b+1;

initial
#10 $stop;
endmodule

You can also check more verilog code on

http://kaneriadhaval.blogspot.in/2013/11/all-besic-verilog-code.html

verilog code for n-bit gray to binary converter

N-BIT  GRAY TO BINARY CONVERTER

module binary2gray #(parameter n=4)
(
input [n-1:0] g,
output [n-1:0] b
);
assign b={g[n],b[n:1]^g[n-1:0]};
endmodule

TESTBENCH

module binary2gray_tb;
parameter n=4;
reg [n-1:0]g;
wire [n-1:0]b;
binary2gray b2g(.b(b),.g(g));
initial
begin
#1 g=4'b1111;
$monitor($time,  ,"gra","y","%b",g, ,"bin","ary","%b",b);
end

always

#1 g=g+1;

initial
#10 $stop;
endmodule

You can also check more verilog code on

http://kaneriadhaval.blogspot.in/2013/11/all-besic-verilog-code.html

verilog code for d-latch using dataflow

·         D LATCH USING DATAFLOW

module latch_d
(input e, D,
output Q);
assign Q=e&D;
endmodule


TESTBENCH

module latch_d_tb;
reg e,D;
wire q;
latch_d m(e,D,q);
initial
begin
e=0;D=0;
$monitor($time, ,,"e=%b",e,,"D=%b",D,,"q=%b",q);
#1 e=0;D=0;
#1 e=1;D=0;
#1 e=0;D=1;
#1 e=1;D=1;
end
endmodule

You can also check more verilog code on

http://kaneriadhaval.blogspot.in/2013/11/all-besic-verilog-code.html

verilog code for bcd to binary

BCD TO BINARY


module bcd2binary
(input [7:0]bcd,
output reg[3:0]binary);

always@(bcd)
begin
if(bcd[3:0]<4'b1010)
begin
if(bcd[7:4]=={4{1'b0}})
binary=bcd[3:0];
if((bcd[7:5]=={3{1'b0}})&&(bcd[4]==1'b1))
binary=bcd[3:0]+4'b1010;
end
else
binary={4{1'bx}};

end
endmodule

TEST BENCH

module bcd2binary_tb;
reg [7:0]bcd;
wire [3:0]binary;

bcd2binary b1(bcd,binary);
initial
begin
bcd=8'b00000000;
$monitor($time, ,"bcd", ,"%b",bcd,  , "bin","ary", ,"%b",binary);
end

always
#1 bcd=bcd+1;

initial
#22 $stop;
endmodule

You can also check more verilog code on

http://kaneriadhaval.blogspot.in/2013/11/all-besic-verilog-code.html

Use of include guard in c or c++

USE OF INCLUDE GUARD

Header files are often of the form

    #ifndef FOO
     #define FOO
     ...
     #endif

to prevent the compiler from processing them more than once. The preprocessor notices such header files, so that if the header file appears in a subsequent #include directive and FOO is defined, then it is ignored and it doesn't preprocess or even re-open the file a second time. This is referred to as the multiple include optimization.

For example,

 lets say you have two header files, a.h and b.h. The header file b.h includes a.h, and then both a.h and b.h is included in the source file s.c. Without header guards the file a.h will be included twice, which can cause errors. If the header files had header guards then the file a.h would only be included once.

You don't need header guards in source files because usually you don't include them in other files.

In CeePlusPlus you can guard against a header file being included more than once with what is called an IncludeGuard.

A naive compiler will reload the file every time it's included. To avoid that, put RedundantIncludeGuards around the include:

header.h

  #ifndef HEADER_H_
  #define HEADER_H_
  // declarations
  #endif

foo.c

  #ifndef HEADER_H_
  #include "header.h"
  #endif

If the preprocessor sees this sequence after once including header.h (and therefore defining HEADER_H_) it will skip over the #include directive entirely - without scanning, or even opening, header.h.

This example is slightly misleading. Note:

Using Redundant Include Guards in implementation files has much less gain than doing the same in a header, and adds quite a bit more confusion due to the usually larger number of includes there.

In other words:

header.h

  #ifndef HEADER_H_
  #define HEADER_H_
  // declarations
  #endif

fooheader.h

  #ifndef HEADER_H_
  #include "header.h"
  #endif