verilog code for counter

COUNTER INCREMENT BY 2

module counter2(r,clk,y);
input r,clk;
output [3:0]y;
reg [3:0]y;
always@(posedge clk or posedge r)
begin
if (r)
y <= 4'b0000;
else
y <= y + 2;
end
endmodule

TESTBENCH

module counter3_tb;
reg r,clk;
wire [3:0]y;
counter2 m1(r,clk,y);
initial
begin
clk=0;
r=0;
$monitor($time, ,,"c=%b",clk,,"r=%b",r,,"y=%b",y);
#5 r=1;
#15 r=0;
#50 $finish;
end
always
begin
#5 clk=~clk;
end
endmodule

OUTPUT



·         COUNTER INCREMENT BY 3

module counter2(r,clk,y);
input r,clk;
output [3:0]y;
reg [3:0]y;
always@(posedge clk or posedge r)
begin
if (r)
y <= 4'b0000;
else
y <= y + 3;
end
endmodule

TESTBENCH

module counter3_tb;
reg r,clk;
wire [3:0]y;
counter2 m1(r,clk,y);
initial
begin
clk=0;
r=0;
$monitor($time, ,,"c=%b",clk,,"r=%b",r,,"y=%b",y);
#5 r=1;
#15 r=0;
#50 $finish;
end
always
begin
#5 clk=~clk;
end
endmodule

You can also check more verilog code on

http://kaneriadhaval.blogspot.in/2013/11/all-besic-verilog-code.html