Overflow rule checking with verilog code with test bench

 I implimented this code in xilinx . it will check overflow condition in 2  8-bit number in 2's compliment form in addition.

2

VERILOG MODULE

`timescale 1ns / 1ps

module overflow(

    input [7:0] a,

    input [7:0] b,

    output reg c,

    output reg[7:0] d

    );

                always @ (a or b)

                begin

                d = a + b;

               

                if ((a[7] == b[7]) && (b[7] == d[7]) && (a[7] == d[7]))

                                                c = 1;

                else if ((a[7] == b[7]) && (b[7] != d[7]) && (a[7] != d[7]))

                                                begin

                                                c = 0;

                                                d = 8'bxxxxxxxx;

                                                end

                else

                begin

                                                c = 1;

                                                end

               

                end

endmodule

2.       VERILOG TEXT FIXTURE

`timescale 1ns / 1ps

module overflow_tb;

reg [7:0] a,b;

wire c;

wire [7:0] d;

overflow m1(a,b,c,d);

initial

begin

a=8'b00000000;

b=8'b00000000;

#5 a=8'b00001111; b=8'b11111000;

#5 a=8'b11110000; b=8'b01110100;

#5 a=8'b11001111; b=8'b00110100;

#5 a=8'b10001100; b=8'b01100100;

#5 a=8'b11001111; b=8'b10000100;

#5 a=8'b10000000; b=8'b11110100;

#100 $finish;

end

endmodule