Thursday, 14 November 2013

besic verilog code

hello friends....

after a long time i came to u with some usefull verilog code with test bench.every time i came across some besic verilog code which frequently asked in colleges,company etc...so decided to provide u all verilog code with test bench .i used for cver tool for compile and run code in ubuntu system.

cver tool is a software for compile and run verilog code in ubuntu..u can also generate waveform file in gtkwave tool.                         
BY KANERIA DHAVAL

·        
JK FLIPFLOP

module jkff(jk,pst,clr,clk,qp,qbar);
    input [1:0] jk;    input pst,clr,clk;
    output qp,qbar;
    reg qp;    wire q;
    always @ (posedge clk)
     if (pst)
               qp= 1;
            else
                        begin
                        if (clr)
                          qp= 0;
                        else
                           begin
                           case (jk)
                               2'b00: qp=q;
                                      2'b01 : qp = 1'b0;
                                      2'b10  : qp =1'b1;
                                      2'b11 : qp = ~q;
                                      default qp =0;
                                    endcase
                                    end
                        end
             assign qbar = ~q;
             assign q = qp;
endmodule








TESTBENCH

module jkff_tb;
reg [1:0]jk;
reg pst,clr,clk;
wire qp,qbar,q;

jkff j1(jk,pst,clr,clk,qp,qbar);
initial
begin
$monitor($time,  ,,"t=%b",clk,,"p=%b",pst,,"c=%b",clr,,"j=%b",jk,,"q=%b",qp, ,"z=%b",qbar);
pst=0;
clr=0;
clk=0;
#5 jk=2'b00;
#5 jk=2'b00;pst=1;
#5 jk=2'b10;pst=0;clr=1;
#5 jk=2'b00;clr=0;
#5 jk=2'b01;clr=0;
#5 jk=2'b10;clr=0;
#5 jk=2'b11;clr=0;
#10 $finish;
end

always
   begin
#5 clk=~clk;

   end
endmodule

OUTPUT




T FLIPFLOP
module tff_qn(t, clk, reset, q,qn);
input  t, reset, clk;
output           q,qn;
reg      q,qn;
            always  @( posedge clk or reset)
                        if (reset)
                        q<=1'b0;
                        else
                        q<=q^t;
            always @(q)
            qn<=~q;
endmodule







TESTBENCH

module tff_qn_tb;
reg t, reset, clk;
wire q,qn;
tff_qn m1(t,clk,reset,q,qn);
initial
begin
t=0;reset=0;clk=1;
$monitor($time, ,,"c=%b",clk,,"r=%b",reset,,"t=%b",t,,"q=%b",q);
#5 t=1;reset=0;
#15 t=1;reset=0;
#25 t=0;reset=1;
#35 t=1;reset=0;
#30 $finish;
end
always
begin
#5 clk=~clk;
end
endmodule

OUTPUT



 D FLIPFLOP

module dff(d,clk,q,qbar);
    input d;
    input clk;
    output q,qbar;
    reg q, qbar;
    always @ (posedge clk)
         begin
                        q = d;
                        qbar = ~d;
end
endmodule

TESTBENCH

module dff_tb;
reg d,clk;
wire q,qbar;
dff m1(d,clk,q,qbar);
initial
begin
d=0;clk=1;
$monitor($time, ,,"c=%b",clk,,"d=%b",d,,"q=%b",q,,"z=%b",qbar);
#5 d=0;
#5 d=1;
#5 d=0;
#5 d=1;
#15 $finish;
end
always
begin
#5 clk=~clk;
end
endmodule





OUTPUT



·         UNIVERSAL SHIFT REGISTER

module sreg(data,rin,lin, s,q,clock, reset);
input clock,reset, rin, lin;
input [1:0] s;
input [3:0] data;
output [3:0] q;
reg [3:0] q;
always @(posedge clock or posedge reset)
begin
if (reset) q<=4'b0000;
else
begin
case(s)
2'b00: q<=q;
2'b01: q<={rin,q[3:1]};
2'b10:  q<={q[2:0],lin};
2'b11: q<=data;
default: q<=4'b0000;
endcase
end
end
endmodule

TESTBENCH

module sreg_tb;
reg clock,reset, rin, lin;
reg[1:0] s;
reg [3:0] data;
wire [3:0] q;
sreg m1(data,rin,lin, s,q,clock, reset);
initial
begin
clock=0;reset=0;s=0;rin=0;lin=0;data=4'b0000;
$monitor($time, ,,"c=%b",clock,,"e=%b",reset,,"s=%b",s,,"r=%b",rin,,"l=%b",lin,,"d=%b",data,,"q=%b",q);
#0 reset=1;s=0;rin=0;lin=0;data=4'b1010;
#5 reset=0;s=2'b11;rin=0;lin=0;data=4'b1010;
#10 reset=0;s=2'b01;rin=1;lin=0;data=4'b1010;
#15 reset=0;s=2'b10;rin=0;lin=1;data=4'b1010;
#30 $finish;
end
always
begin
#5 clock=~clock;
end
endmodule






OUTPUT



·         4-BIT UNIVERSAL(UP-DOWN) COUNTER

//universal counter includes up & down counter
module universal
(input clk,rst,up_down,
output reg [3:0] q);
always@(posedge clk,negedge rst)
begin
if(!rst)
q<=4'b0000;
else if(up_down)
q<=q+1;
else
q<=q-1;
end
endmodule


TESTBENCH

module universal_tb;
reg clk,rst,up_down;
wire [3:0]q;
universal u1(clk,rst,up_down,q);
initial
begin
rst = 0;
up_down = 1;
clk=1;
$monitor($time,,,"c=%b",clk,,"u=%b",up_down,,"r=%b",rst,,"q=%b",q);
#5 rst =1;
#60 up_down=0;
#100 $finish;
end
always
begin
#5 clk =~clk;
end
endmodule

OUTPUT

·         BINARY TO BCD CONVERTER

module binary2bcd
(input[3:0] binary,
output reg[7:0]bcd);

always@(binary)
begin
bcd=4'b00000000;
if((binary[3]==1&&(binary[2]==1||binary[1]==1)))
begin
bcd=binary-4'b1010;
bcd[4]=1;
end
else if(((binary[3]==1||binary[3]==0)&&binary[2]==0&&binary[1]==0))
begin
bcd[3]=binary[3];bcd[2]=binary[2];bcd[1]=binary[1];bcd[0]=binary[0];
end
else if(binary[3]==0)
begin
bcd[3]=binary[3];bcd[2]=binary[2];bcd[1]=binary[1];bcd[0]=binary[0];
end
else
;
end
endmodule

TESTBENCH

module binary2bcd_tb;
reg[3:0]binary;
wire[7:0]bcd;

binary2bcd b2b(binary,bcd);
initial
begin
binary=4'b0000;
$monitor($time, ,"bin      ", ,binary[3],binary[2],binary[1],binary[0], ,"bcd",  ,bcd[7],bcd[6],bcd[5],bcd[4],  ,bcd[3],bcd[2],bcd[1],bcd[0]);
while(binary!=4'b1111)
#1 binary=binary+1;
end
endmodule
OUTPUT


·         4 BIT MAGNITUDE COMPARETOR
module magnitudeComparator(
input [3:0]A,B,
output reg equal,greater,lesser);
reg [3:0]x;

always@(A,B)
begin
x=A~^B;
equal=x[3]&x[2]&x[1]&x[0];
greater=(A[3]&(~B[3]))|(x[3]&A[2]&(~B[2]))|(x[3]&x[2]&A[1]&~B[1])|(x[3]&x[2]&x[1]&A[0]&~B[0]);
lesser=(~A[3]&B[3])|(x[3]&~A[2]&B[2])|(x[3]&x[2]&~A[1]&B[1])|(x[3]&x[2]&x[1]&~A[0]&B[0]);

end
endmodule

TESTBENCH

module magnitudeComparator_tb;
reg [3:0]A,B;
wire equal,greater,lesser;

magnitudeComparator mc(A,B,equal,greater,lesser);

initial
begin
A=4'b1111;B=4'b1111;
$monitor($time, ,"A=%b",A,"(",A,")",   ,"B=%b",B,"(",B,")",  ,"A==B", ,equal, ,"A>B", ,greater, ,"A<B", ,lesser);
#1 A=4'b1110;
#1 B=4'b1101;
end
endmodule


OUTPUT


RING COUNTER
module ring_count(q,clk,clr);
  input clk,clr;
  output [3:0]q;
  reg [3:0]q;
  always @(posedge clk)
       if(clr==1)
            q<=4'b1000;
        else
            begin
                q[3]<=q[0];
                q[2]<=q[3];
                q[1]<=q[2];
                q[0]<=q[1];
            end
endmodule

TESTBENCH

module ring_count_tb;
reg clk,clr;
wire [3:0]q;
ring_count m1(q,clk,clr);
initial
begin
$monitor($time, ,,"t=%b",clk,,"c=%b",clr,,"q=%b",q);
clr=1'b0;clk=1'b0;
#50 clr=1'b1;
#100 clr=1'b0;
#500 $finish;
end
always
   begin
#50 clk=~clk;
   end
endmodule



OUTPUT


JOHNSON COUNTER

module jc(clk, state);
input clk;
output [3:0] state;
reg [3:0] state;
initial state <= 0;
always@(posedge clk)
begin
case (state)
4'b0000: state <= 4'b1000;
4'b1000: state <= 4'b1100;
4'b1100: state <= 4'b1110;
4'b1110: state <= 4'b1111;
4'b1111: state <= 4'b0111;
4'b0111: state <= 4'b0011;
4'b0011: state <= 4'b0001;
4'b0001: state <= 4'b0000;
endcase
end
endmodule

TESTBENCH

module jc_tb;
reg clk;
wire [3:0]state;
jc m1(clk,state);
initial
begin
$monitor($time, ,,"t=%b",clk,,"s=%b",state);
clk=1'b1;
#90 $finish;
end
always
   begin
#5 clk=~clk;
  end
endmodule


·         MULTIPLIER

module multiplier(input [7:0]a,b, output reg[15:0]c );
always@(a,b)
begin
if((a==8'b0)||(b==8'b0))
c=16'b0;
else
c=a*b;
end
endmodule

TESTBENCH

module multiplier_tb;
reg [7:0]a,b;
wire [15:0]c;

multiplier mlt(a,b,c) ;

initial
begin
a=8'b00000000; b=8'b00000000;
$monitor($time, ,"a=%b",a, ,"(",a,")",  ,"b=%b",b, ,"(",b,")",  ,"c=%b",c, ,"(",c,")" );
#1 a=8'b00001010;
#1 b=8'b00001010;
#1 b=8'b10001010;
#1 a=8'b11111111;
#1 b=8'b11111111;
end
endmodule

OUTPUT


·          DEVIDER

module divider(input [7:0]a,b, output reg[7:0]q,r );
always@(a,b)
begin
if(b==8'b0)
;
else
q=a/b;
r=a%b;
end
endmodule

Testbench:

module divider_tb;
reg [7:0]a,b;
wire [7:0]q,r;

divider div(a,b,q,r) ;

initial
begin
a=8'b00000000; b=8'b00001010;
$monitor($time, ,"num=", ,"%b",a, ,"(",a,")",  ,"den=", ,"%b",b, ,"(",b,")",  ,"quo=", ,"%b",q, ,"(",q,")", ,"rem=", ,"%b",r, ,"(",r,")"   );
#1 a=8'b00001010;
#1 b=8'b00001010;
#1 b=8'b10001010;
#1 a=8'b11111111;
#1 b=8'b11111111;
end
endmodule

OUTPUT




·         COUNTER INCREMENT BY 2

module counter2(r,clk,y);
input r,clk;
output [3:0]y;
reg [3:0]y;
always@(posedge clk or posedge r)
begin
if (r)
y <= 4'b0000;
else
y <= y + 2;
end
endmodule

TESTBENCH

module counter3_tb;
reg r,clk;
wire [3:0]y;
counter2 m1(r,clk,y);
initial
begin
clk=0;
r=0;
$monitor($time, ,,"c=%b",clk,,"r=%b",r,,"y=%b",y);
#5 r=1;
#15 r=0;
#50 $finish;
end
always
begin
#5 clk=~clk;
end
endmodule

OUTPUT



·         COUNTER INCREMENT BY 3

module counter2(r,clk,y);
input r,clk;
output [3:0]y;
reg [3:0]y;
always@(posedge clk or posedge r)
begin
if (r)
y <= 4'b0000;
else
y <= y + 3;
end
endmodule

TESTBENCH

module counter3_tb;
reg r,clk;
wire [3:0]y;
counter2 m1(r,clk,y);
initial
begin
clk=0;
r=0;
$monitor($time, ,,"c=%b",clk,,"r=%b",r,,"y=%b",y);
#5 r=1;
#15 r=0;
#50 $finish;
end
always
begin
#5 clk=~clk;
end
endmodule

      




MASTERSLAVE JK FLIPFLOP USING STRUCTURAL MODELING

module msjk
(input wire j,k,clk,rst,prst,
output wire q);

jkff jk1(.j(j),.k(k),.clk(clk),.rst(rst),.prst(prst),.q(w));
jkff jk2(.j(w),.k(~w),.clk(~clk),.rst(rst),.prst(prst),.q(q));

endmodule

TESTBENCH

module jkff
(input wire j,k,clk,rst,prst,
output reg q);

always@(posedge clk,negedge rst,posedge prst)

begin
            if(~rst)
            q<=0;
            else if(prst)
            q<=1;
            else if(clk)
            q<=((j&~q)+(~k&q));
            else if(~clk)
            q<=q;
            else
            ;
             
end
endmodule
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2 comments:

  1. Unknown14 November 2013 at 13:52

    there are mistakes in some of the codes dear

    ReplyDelete
  2. Unknown4 April 2020 at 01:05

    Could you help me in Verilog 8 bit binary to gray and vice versa with wave simulation
    vision29gupta@gmail.com

    ReplyDelete

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