verilog code for candy vending machine

hello friends....
I am providing u verilog code for candy vending machine with test bench.

CANDY MACHINE

module candy(d,n,q, reset, clk, y);
output reg y;
input d,n,q;    //n=5,d=10,q=25;
input clk;
input reset;
reg [2:0] cst, nst;
parameter S0 = 3'b000,
          S1 = 3'b001,
          S2 = 3'b010,
          S3 = 3'b100,
              S4 = 3'b101,
              S5 = 3'b110,
              S6 = 3'b111;
always @(cst or d or n or q)
 begin
 case (cst)
   S0: if (n== 1'b1 && d==1'b0 && q==1'b0)
            begin
         nst = S1;
             y=1'b0;
            end
      else if(n== 1'b0 && d==1'b1 && q==1'b0)
            begin
            nst=S2;
            y=1'b0;
            end
            else if(n== 1'b0 && d==1'b0 && q==1'b1)
            begin
            nst=S5;
            y=1'b0;
            end
             else
            begin
            nst = cst;
            y=1'b0;
            end
   S1: if (n== 1'b1 && d==1'b0 && q==1'b0)
            begin
         nst = S2;
             y=1'b0;
            end
      else if(n== 1'b0 && d==1'b1 && q==1'b0)
            begin
            nst=S3;
            y=1'b0;
            end
            else if(n== 1'b0 && d==1'b0 && q==1'b1)
            begin
            nst=S6;
            y=1'b0;
            end
             else
            begin
            nst = cst;
            y=1'b0;
            end
   S2:if (n== 1'b1 && d==1'b0 && q==1'b0)
            begin
         nst = S3;
             y=1'b0;
            end
      else if(n== 1'b0 && d==1'b1 && q==1'b0)
            begin
            nst=S4;
            y=1'b0;
            end
            else if(n== 1'b0 && d==1'b0 && q==1'b1)
            begin
            nst=S0;
            y=1'b1;
            end
             else
            begin
            nst = cst;
            y=1'b0;
            end
   S3: if (n== 1'b1 && d==1'b0 && q==1'b0)
            begin
         nst = S4;
             y=1'b0;
            end
      else if(n== 1'b0 && d==1'b1 && q==1'b0)
            begin
            nst=S5;
            y=1'b0;
            end
            else if(n== 1'b0 && d==1'b0 && q==1'b1)
            begin
            nst=S0;
            y=1'b1;
            end
             else
            begin
            nst = cst;
            y=1'b0;
            end
S4: if (n== 1'b1 && d==1'b0 && q==1'b0)
            begin
         nst = S5;
             y=1'b0;
            end
      else if(n== 1'b0 && d==1'b1 && q==1'b0)
            begin
            nst=S6;
            y=1'b0;
            end
            else if(n== 1'b0 && d==1'b0 && q==1'b1)
            begin
            nst=S0;
            y=1'b1;
            end
             else
            begin
            nst = cst;
            y=1'b0;
            end
S5: if (n== 1'b1 && d==1'b0 && q==1'b0)
            begin
         nst = S6;
             y=1'b0;
            end
      else if(n== 1'b0 && d==1'b1 && q==1'b0)
            begin
            nst=S0;
            y=1'b1;
            end
            else if(n== 1'b0 && d==1'b0 && q==1'b1)
            begin
            nst=S0;
            y=1'b1;
            end
             else
            begin
            nst = cst;
            y=1'b0;
            end
S6: if (n== 1'b1 && d==1'b0 && q==1'b0)
            begin
         nst =S0;
             y=1'b1;
            end
      else if(n== 1'b0 && d==1'b1 && q==1'b0)
            begin
            nst=S0;
            y=1'b1;
            end
            else if(n== 1'b0 && d==1'b0 && q==1'b1)
            begin
            nst=S0;
            y=1'b1;
            end
             else
            begin
            nst = cst;
            y=1'b0;
            end
                       
   default: nst = S0;
  endcase
end
always@(posedge clk) //or posedge reset)
begin
 if (reset)
   cst <= S0;
 else
   cst <= nst;
end
endmodule

TEST BENCH

module candy_tb;
reg n,d,q,clk,reset;
wire y;
candy m1(n,d,q,reset, clk, y);
initial
begin
reset=0          ;clk=0;n=0;q=0;d=0;
$monitor($time, , ,"c=%b",clk,,"y=%b",y,,"r=%b",reset,,"d=%b",d,,"n=%b",n,,"q=%b",q);
#10 d=0;n=1;q=0;
#10 d=1;n=0;q=0;
#10 d=1;n=0;q=0;
#10 d=0;n=1;q=0;
#10 d=0;n=1;q=0;
#10 d=0;n=1;q=0;
#10 d=0;n=1;q=0;
#10 d=0;n=1;q=0;
#10 d=0;n=0;q=0;
end
always
#5 clk=~clk;
initial
#100 $finish ;

endmodule

verilog code for washing machine

hello guys....

i am providing u a verilog code for washing machine with testbench....

WASHING MACHINE

module wm(clk,rst,coin, lid_r, d_wash, T, soak,rinse, spin, wash,pause,break);
 input clk,rst,coin,lid_r,d_wash,T;
 output reg soak,rinse,spin,wash,pause,break;
 reg[2:0] cst, nst;

 // state assignment
 parameter IDLE = 3'b000,
           SOAK = 3'b001,
             WASH=3'b010,
             RINSE=3'b011,
             WASH2=3'b100,
             RINSE2=3'b101,
             SPIN=3'b110,
             PAUSH=3'b111;

always @(cst or coin or d_wash or lid_r or T)
begin
   case (cst)
     IDLE:
if(coin==1)
          begin
          nst=SOAK;
          soak=1;
          rinse=0;
          spin=0;
          wash=0;
          pause=0;
          break=0;
          end
else

          begin
          nst=cst;
          soak=0;
          rinse=0;
          spin=0;
          wash=0;
          pause=0;
          break=0;
          end

SOAK:
if(T==1)

          begin
          nst=WASH;
          soak=0;
          rinse=0;
          spin=0;
          wash=1;
          pause=0;
          break=0;
          end
else
          begin
          nst=cst;
          soak=1;
          rinse=0;
          spin=0;
          wash=0;
          pause=0;
          break=0;
          end
     WASH:
if(T==1)

          begin
          nst=RINSE;
          soak=0;
          rinse=1;
          spin=0;
          wash=0;
          pause=0;
          break=0;
          end
else
          begin
          nst=cst;
          soak=0;
          rinse=0;
          spin=0;
          wash=1;
          pause=0;
          break=0;
          end
RINSE:
if(T==1 && d_wash==1)

          begin
          nst=WASH2;
          soak=0;
          rinse=0;
          spin=0;
          wash=1;
          pause=0;
          break=0;
          end
else if(T==1 && d_wash==0)

          begin
          nst=SPIN;
          soak=0;
          rinse=0;
          spin=1;
          wash=0;
          pause=0;
          break=0;
          end
else
          begin
          nst=cst;
          soak=0;
          rinse=1;
          spin=0;
          wash=0;
          pause=0;
          break=0;
          end
WASH2:
if(T==1)

          begin
          nst=RINSE2;
          soak=0;
          rinse=1;
          spin=0;
          wash=0;
          pause=0;
          break=0;
          end
else
          begin
          nst=cst;
          soak=0;
          rinse=0;
          spin=0;
          wash=1;
          pause=0;
          break=0;
          end

RINSE2:
if(T==1)
          begin
          nst=SPIN;
          soak=0;
          rinse=0;
          spin=1;
          wash=0;
          pause=0;
          break=0;
          end
else
          begin
          nst=cst;
          soak=0;
          rinse=1;
          spin=0;
          wash=0;
          pause=0;
          break=0;
          end
SPIN:
if(T==0 && lid_r==1)
          begin
          nst=PAUSH;
          soak=0;
          rinse=0;
          spin=0;
          wash=0;
          pause=1;
          break=0;
          end
else if(T==1)
          begin
          nst=IDLE;
          soak=0;
          rinse=0;
          spin=0;
          wash=0;
          pause=0;
          break=0;
          end
else
          begin
          nst=cst;
          soak=0;
          rinse=0;
          spin=1;
          wash=0;
          pause=0;
          break=0;
          end
PAUSH:
if(lid_r==0)
          begin
          nst=SPIN;
          soak=0;
          rinse=0;
          spin=1;
          wash=0;
          pause=0;
          break=0;
          end
else
          begin
          nst=cst;
          soak=0;
          rinse=0;
          spin=0;
          wash=0;
          pause=1;
          break=0;
          end
     default:
nst=IDLE;
   endcase
  end
always @(posedge clk or negedge rst)
begin
   if (rst)
     cst <= IDLE;
    else
     cst <= nst;
 end
/*
  assign soak = (cst == SOAK);
  assign rinse = (cst == RINSE) | (cst == RINSE2);
  assign brake = (cst == PAUSE);
  assign spin = (cst == SPIN);
  assign wash = (cst == WASH) | (cst == WASH2);
*/
endmodule

TEST BENCH

module wm_tb;
reg clk,reset,coin,lid_r,d_wash,T;
wire soak,rinse,spin,wash,pause,break;
wm m1(clk,reset,coin,lid_r,d_wash,T,soak,rinse,spin,wash,pause,break);
initial
begin

$monitor($time, ,,"c=%b",clk,,"t=%b",coin,,"l=%b",lid_r,,"d=%b",d_wash,,"T=%b",T,,"s=%b",soak,,"r=%b",rinse,,"S=%b",spin,,"w=%b",wash,,"p=%b",pause,,"b=%b",break);
reset=0       ;clk=0;coin=0;lid_r=0;d_wash=0;T=0;
#10 coin=1;
#10 T=1;coin=0;
#20 d_wash=1;
#30 lid_r=1;d_wash=0;T=0;
#10 lid_r=0;T=0;
#10 T=1;lid_r=0;
#10 T=1;
#10 coin=1;T=0;
//#10 T=1;
//#10 T=1;
//#5 reset=1;
//#5 reset=0;
end
always
#5 clk=~clk;
initial
#100 $finish ;

endmodule

FSM code in verilog for 1010 sequence detector

hello friends...

i am providing u some verilog code for finite state machine (FSM).i provide code of 1010 sequence detector using mealy machine and moore machine using overlap and without overlap and testbenches.

1010 SEQUENCE DETECTOR

MEALY WITHOUT OVERLAP

module melfsm(din, reset, clk, y);
input din;
input clk;
input reset;
output reg y;
reg [1:0] cst, nst;
parameter S0 = 2'b00, //all state
          S1 = 2'b01,
          S2 = 2'b10,
          S3 = 2'b11;
always @(cst or din)
 begin
 case (cst)
   S0: if (din == 1'b1)
          begin
         nst = S1;
          y=1'b0;
          end
      else
          begin
          nst = cst;
          y=1'b0;
          end
   S1: if (din == 1'b0)
          begin
        nst = S2;
          y=1'b0;
          end
       else
          begin
          y=1'b0;
           nst = cst;
          end
   S2: if (din == 1'b1)
          begin
         nst = S3;
          y=1'b0;
          end    
          else
          begin
          nst = S0;
          y=1'b0;
          end
   S3: if (din == 1'b0)
          begin
         nst = S0;
          y=1'b1;                //output will come
          end
       else
          begin
          nst = S1;
          y=1'b0;
          end
   default: nst = S0;
  endcase
end
always@(posedge clk)
          begin
           if (reset)
             cst <= S0;
           else 
             cst <= nst;
          end
endmodule

TESTBENCH

module melfsm_tb;
reg din,clk,reset;
wire y;
melfsm m1(din, reset, clk, y);
initial
begin
reset=0       ;clk=0;din=0;
$monitor($time, , ,"c=%b",clk,,"y=%b",y,,"r=%b",reset,,"d=%b",din);
#5 din=1;
#5 din=1;
#5 din=1;
#10 din=0;
#10 din=1;
#10 din=0;
#10 din=1;
#10 din=0;
#5 din=1;
//#5 reset=1;
//#5 reset=0;

end
always
#5 clk=~clk;
initial
#80 $finish ;
endmodule

MEALY WITH OVERLAP

module melfsmolp(din, reset, clk, y);
output reg y;
input din;
input clk;
input reset;
reg [1:0] cst, nst;
parameter S0 = 2'b00,
          S1 = 2'b01,
          S2 = 2'b10,
          S3 = 2'b11;
always @(cst or din)
 begin
 case (cst)
   S0: if (din == 1'b1)
          begin
         nst = S1;
          y=1'b0;
          end
      else
          begin
           nst = cst;
          y=1'b0;
          end
   S1: if (din == 1'b0)
          begin
        nst = S2;
          y=1'b0;
          end
       else
          begin
           nst = cst;
          y=1'b0;
          end
   S2: if (din == 1'b1)
          begin
         nst = S3;
          y=1'b0;
          end    
            else
          begin
           nst = S0;
          y=1'b0;
          end
   S3: if (din == 1'b0)
          begin
         nst = S2;
          y=1'b1;
          end
       else
          begin
          nst = S1;
          y=1'b0;
          end
   default: nst = S0;
  endcase
end
always@(posedge clk)
begin
           if (reset)
             cst <= S0;
           else
             cst <= nst;
end
endmodule

TESTBENCH

module melfsmolp_tb;
reg din,clk,reset;
wire y;
melfsmolp m1(din, reset, clk, y);
initial
begin
reset=0       ;clk=0;din=0;
$monitor($time, , ,"c=%b",clk,,"y=%b",y,,"r=%b",reset,,"d=%b",din);
#10 din=1;
#10 din=0;
#10 din=1;
#10 din=0;
#10 din=1;
#10 din=0;
#10 din=1;
#10 din=1;
#10 din=1;
#10 din=0;
#10 din=1;
//#5 reset=1;
//#5 reset=0;
end
always
#5 clk=~clk;
initial
#100 $finish ;
endmodule


MOORE WITHOUT OVERLAP

module morfsm(din, reset, clk, y);
output reg y;
input din;
input clk;
input reset;
reg [2:0] cst, nst;
parameter S0 = 3'b000,
          S1 = 3'b001,
          S2 = 3'b010,
          S3 = 3'b100,
            S4 = 3'b101;
always @(cst or din)
 begin
 case (cst)
   S0: if (din == 1'b1)
          begin
         nst = S1;
          y=1'b0;
          end
      else
          begin
          nst = cst;
          y=1'b0;
          end  
S1: if (din == 1'b0)
          begin
        nst = S2;
          y=1'b0;
          end
       else
          begin
          nst = cst;
          y=1'b0;
          end
   S2: if (din == 1'b1)
          begin
         nst = S3;
          y=1'b0;
          end    
            else
          begin
          nst = S0;
          y=1'b0;
          end  
S3: if (din == 1'b0)
          begin
         nst = S4;
          y=1'b0;
          end
       else
          begin
          nst = S1;
          y=1'b0;
          end
S4: if (din == 1'b0)
          begin
         nst = S0;
          y=1'b1;
          end
          else
          begin
          nst = S1;
          y=1'b1;
          end
   default: nst = S0;
  endcase
end
always@(posedge clk)
begin
 if (reset)
   cst <= S0;
 else
   cst <= nst;
end
endmodule

TESTBENCH

module morfsm_tb;
reg din,clk,reset;
wire y;
morfsm m1(din, reset, clk, y);
initial
begin
reset=0       ;clk=0;din=0;
$monitor($time, , ,"c=%b",clk,,"y=%b",y,,"r=%b",reset,,"d=%b",din);
#10 din=1;
#10 din=1;
#10 din=1;
#10 din=0;
#10 din=1;
#10 din=0;
#10 din=1;
#10 din=0;
#10 din=1;
//#5 reset=1;
//#5 reset=0;

end
always
#5 clk=~clk;
initial
#100 $finish ;
endmodule


MOORE WITH OVERLAP

module morfsmolp(din, reset, clk, y);
input din;
input clk;
input reset;
output reg y;
reg [2:0] cst, nst;
parameter S0 = 3'b000,
          S1 = 3'b001,
          S2 = 3'b010,
          S3 = 3'b100,
            S4 = 3'b101;
always @(cst or din)
 begin
 case (cst)
   S0: if (din == 1'b1)
          begin
         nst = S1;
          y=1'b0;
          end
      else nst = cst;
   S1: if (din == 1'b0)
          begin
        nst = S2;
          y=1'b0;
          end
       else
          begin
          nst = cst;
          y=1'b0;
          end
   S2: if (din == 1'b1)
          begin
         nst = S3;
          y=1'b0;
          end    
            else
          begin
          nst = S0;
          y=1'b0;
          end
   S3: if (din == 1'b0)
          begin
         nst = S4;
          y=1'b0;
          end
       else
          begin
          nst = S1;
          y=1'b0;
          end
S4: if (din == 1'b0)
          begin
         nst = S1;
          y=1'b1;
          end
          else
          begin
          nst = S3;
          y=1'b1;
          end
   default: nst = S0;
  endcase
end
always@(posedge clk)
begin
          if (reset)
          cst <= S0;
          else
            cst <= nst;
end
endmodule

TESTBENCH

module morfsmolp_tb;
reg din,clk,reset;
wire y;
morfsmolp m1(din, reset, clk, y);
initial
begin
reset=0       ;clk=0;din=0;
$monitor($time, , ,"c=%b",clk,,"y=%b",y,,"r=%b",reset,,"d=%b",din);
#10 din=1;
#10 din=1;
#10 din=1;
#10 din=0;
#10 din=1;
#10 din=0;
#10 din=1;
#10 din=0;
#10 din=1;
//#5 reset=1;
//#5 reset=0;
end
always
#5 clk=~clk;
initial
#100 $finish ;
endmodule